A High-Throughput Asynchronous Pipeline Style Using a Transition-Signaling Protocol
Pipelines are data processing elements in series, in which output from one element is sent as the input to the next element, and are used for computing. Improving computing power and speed is a major requirement for reducing electronic size and weight, which technologies such as wearables, laptops, tablets, etc. require. This technology is a circuit design for very high-throughput asynchronous pipelines for static logic implementations. Called “ MOUSETRAP” (Minimal-Overhead Ultra-high-Speed Transition-signaling Asynchronous Pipeline), this technology can handle variable-speed and varied input and output rates, tackling complex processing quickly. In modern technology that has scaled down to dimensions as small as 0.25 um for processing hardware, these pipelines are expected to deliver a throughput of several GHz.
This technology consists of a circuit design methodology for very high-throughput asynchronous digital pipelines, called “MOUSETRAP”. The pipelines have no global clock. Instead, an asynchronous handshaking protocol is employed between the pipeline stages. As a result, the pipelines avoid all overheads and constraints associated with synchronous global clock distribution. This technology includes a general-purpose style where pipeline stages are separated by explicit latches as well as an optimized style with ‘clock-logic’ (or ‘clocked-CMOS’). In this way, no explicit latches are used but a static logic gate in each stage is clocked directly, incorporating full functionality of a latch (passing data, holding data). This technology is key to the high-throughput of the MOUSETRAP pipelines, avoiding the overhead of a return-to-zero phase for communication signals, allowing the use of small and fast transparent D-latches, and allowing higher throughput in steady state operation (i.e. for regular stream of input data and output requests).
This technology has been tested, implementing the asynchronous datapath using the common ‘single-rail bundled’ style. Preliminary data demonstrates that in steady state operation, the pipeline performance is comparable to that of wave pipelines, yet more robust and requiring less design effort.
Patent Pending (WO/2002/035346)
Tech Ventures Reference: IR M01-020