As CMOS circuits continue to miniaturize, analog circuit elements such as inductors and capacitors are unable to scale at the same rate while maintaining quality. In an effort to reduce overall circuit size, this technology offers a method to place parts of a circuit beneath an inductor coil, reducing circuit size by about 50%. This efficient use of space allows for a more diverse range of miniaturized devices such as RFID tags.
Using a phase-locked loop (PLL) design, the capacitor is placed underneath the inductor to save space and shield the inductor from the surrounding circuit currents. Along with carefully planned current paths and magnetic coupling, this design allows for a high quality factor for the inductors while reducing the size of the circuit by about 50%.
Patent Issued (US7847667)
Tech Ventures Reference: IR M05-084