CMOS-compatible full duplex communication system for enhanced wireless network performance

Existing wireless systems operate in half duplex, where transmitted and received signals are separated in either frequency or time. Full duplex (FD) communication has the capacity to significantly increase wireless communication speed and efficiency because it utilizes the same frequency band to both transmit and receive signals. Currently available FD devices either experience a large amount of self-interference or require bulky off-the-shelf components, rendering them incompatible for CMOS implementations. This technology is a robust FD wireless communication system with a self-interference cancelling (SIC) process that can be fabricated using conventional CMOS technology. The technology provides low-cost and efficient means to a FD wireless network. As such, the technology can be incorporated into multiple input, multiple output (MIMO) technology to improve spectral efficiency for next generation wireless communication devices.

Integrated antenna interface for high self-interference suppression of transmitted and received signals

This technology incorporates a SIC method that uses specialized amplifiers in the antenna, analog, and digital domains. The multi-domain approach allows for a superior SIC compared to other FD systems using SIC within a single domain. A joint SIC ensures large overall self-interference suppression and allows one to design the amount of SIC and the SIC bandwidth for various applications. This technology uses a compact form-factor that can be integrated on a single chip. The use of cost-effective CMOS technology will enable widespread implementation of FD communication.

A prototype of the technology has been implemented in 65 nm CMOS technology and has demonstrated a record-high SIC of 85 dB.

Lead Inventor:

Harish Krishnaswamy, Ph.D.

Applications:

  • FD wireless communication system
  • MIMO technology
  • Radio design for next generation telecommunication
  • Two-way communication in bandlimited environments
  • High bit rate Internet access
  • Small form-factor mobile applications

Advantages:

  • Undergoes simultaneous transmission and reception of frequency channel
  • Increases spectrum efficiency
  • Achieves higher limit of SIC
  • Performs joint SIC across domains
  • Uses conventional cost-effective CMOS technology
  • Functions as a compact integrated circuit

Patent Information:

Patent Issued

Tech Ventures Reference: IR CU16171

Related Publications:

Quick Facts:
Tags
65 nm processAnalog signalBasebandBit rateCMOSCompact spaceIntegrated circuitMIMONegative-feedback amplifierRadioSpectral efficiencyTelecommunicationWirelessWireless network
Inventors
Harish KrishnaswamyJin Zhou
Manager
Greg Maskel
Departments
Electrical Engineering
Divisions
Fu Foundation School of Engineering and Applied Science (SEAS)
Reference Number
CU16171
Release Date
2016-10-21