This technology describes a continuous-time analog-to-digital converter (ADC) and digital filter for low-cost and low-power integrated circuit applications.
Wireless receivers, such as those provided in mobile phones, generally comprise an analog-to-digital converter (ADC) that converts the received signal into a digital signal for downstream applications. However, most ADCs employ a discrete-time technique in which the received signal is sampled at the same sampling frequency regardless of the amplitude of the input signal, resulting in constant power consumption by the ADC even when the wireless transmission is spares. In addition, this sampling method risks bringing out-of-band interferers into the signal band, which generally requires an additional antialiasing filter to remove such interferers before sampling. As such, there is a need for an improved ADC having low power consumption even in the presence of such interferers.
This technology proposes a new system and method for power-efficient continuous-time ADCs. Most power consumption in ADCs stems from sampling the input signal and filtering out frequencies outside the useful band or channel. This technology employs continuous-time level-crossing sampling scheme where the ADC does not have to continuously sample the input signal, reducing power consumption. Once the input signal is digitally converted, it is fed into a feedback loop with a digital filter circuit. The purpose of this digital filter feedback loop is to suppress the interferers in the input signal with minimum complexity and power consumption.
This technology has been tested via extensive simulations and testing of chips using various input signals, and easily interfaces with event-driven continuous-time digital signal processing (DSP).
Patent Issued (US 9,344,107)
IR CU16019
Licensing Contact: Greg Maskel