3D chip stacking allows for an exponential increase in component density. Components may be made individually through more sophisticated or less conventional fabrication procedures as desired, and then organized or stacked to improve performance, cost, and power efficiency of the multi-chip system. Electrical connections are conferred between adjacent chips through connection bumps while Connection bumps while being aligned to efficiently pass signal and power to each component. This method of chip integration does not stipulate fabrication procedures, and encourages interposing layers to deliver the benefits of integrating multiple chip connections.
Integration of inductors, switches, and capacitors on a single chip poses significant challenges. This technology allows for integration of unconventional components together with more widely available components in order to reduce costs. In this way, reliable performance in ensured without the additional investment required to modify the platforms of newer, more complex CMOS technologies.
The performance of this technology has been demonstrated by way of models, simulations, and a working prototype of an integrated circuit and interposer with magnetic core inductor.
Patent information:
Patent Pending
Licensing Status:
Available for licensing and sponsored research support
Tech Ventures Reference: IR CU12054
Related Publications:
Further Information: Columbia | Technology Ventures Email: TechTransfer@columbia.edu