This technology is a latchless, asynchronous digital pipeline circuit for high-speed and high throughput applications.
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Unmet Need: Decreased power demands for CPUs and DSPs
Consumer demand for faster, high-quality electronic devices continues to drive markets for smartphones, tablets, and other mobile electronic devices. An ongoing challenge, however, is providing adequate battery life while ensuring high performing devices still provide long-lasting performance.
The Technology: Cost-effective, high throughput asynchronous pipeline with reduced power consumption
This technology is a system for latchless, dynamic asynchronous digital pipelines that are high buffering and high throughput. By using two decoupled inputs, a stage is driven through three distinct phases in sequence to evaluate, isolate, and precharge. In the isolate phase, a stage holds its outputs stable irrespective of any changes in inputs. Adjacent pipeline stages are capable of storing distinct data items without spacers. As a result, this system provides a pipeline having protocols with no explicit latches that have reduced critical delays, smaller chip area, and lower power consumption. This technology thus provides simple, small, and fast control circuits that reduce power consumption and manufacturing costs.
The dynamic pipelines provide 100% buffering capacity, without explicit latches, by means of separate pullup and pulldown control for each pipeline stage: neighboring stages can store distinct data items, unlike almost all existing latchless dynamic pipelines. As a result, very high throughput is obtained. Fabricated first-in/first-out (FIFO) designs, in a 0.18 micron technology, were fully functional over a wide range of supply voltages (1.2 to over 2.5V), exhibiting a corresponding range of throughputs from 1.0-2.4 Giga-items/second.
Applications:
- Mobile devices such as smartphones and tablets
- Laptop computers
- CPU architecture
- High speed DSP
Advantages:
- Enhanced power efficiency
- Latchless design
- Higher storage or buffering capacity
- Low forward latency and easily satisfied one-sided timing constraint
- Reduced cost
- Able to handle varied input and output rates
- These asynchronous pipelines were used in an IBM experimental project [Singh/Tierno/Rylyakov/Rylov/Nowick 2010] to design a low-latency digital finite impulse response (FIR) for disk drive reads. The speed-critical portion of the filter was designed as a high-performance asynchronous pipeline sandwiched between synchronous input and output portions, making it possible for the entire filter to be embedded within a clocked system, and to appear externally as a synchronous filter. A novel feature of the filter is that the degree of pipelining can be dynamically variable, depending upon the input data rate. This capability is directly enabled the internal use of these asynchronous pipelines. This feature is critical in obtaining a very low filter latency throughout the range of operating frequencies. Resulting chips were fully functional over a wide range of supply voltages, and exhibited throughputs of over 1.3 Giga-items/second and latencies of 2-5 clock cycles, in a 0.18 micron CMOS process. Interestingly, the filter throughput was limited by the synchronous portion of the chip; the asynchronous pipeline was estimated to be capable of significantly higher throughputs, around 1.8 Giga-items/second. In addition, the pipelined nature of the filter allows it to offer a worst-case latency of only 10ns, which is half the worst-case latency of the best previously reported comparable fully-synchronous FIR implementation
Lead Inventor:
Steven Nowick, Ph.D.
Patent Information:
Patent Issued (US 7,053,665)
Patent Issued (US 6,867,620)
Related Publications:
M. Singh and S.M. Nowick, “The design of high-performance asynchronous dynamic pipelines: high-capacity style” IEEE Transactions on VLSI Systems, vol. 15:11, pp. 1270-1283 (2007)
M. Singh J. Tierno, A. Rylyakov, S. Rylov and S.M. Nowick,”An adaptively pipelined mixed synchronous-asynchronous digital FIR filter chip operating at 1.3 Gigahertz,” IEEE Transactions on VLSI Systems, vol. 18:7, pp. 1043-1056 (2010)
S.M. Nowick and M. Singh, “High-performance asynchronous pipelines: An overview,” IEEE Design & Test of Computers, vol. 28:5, pp. 8-22 (Sept./Oct. 2011)
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