This technology is an optimization algorithm for asynchronous circuits that can accommodate timing discrepancies, consume less power, and reduce electromagnetic interference in computer-aided design (CAD).
Avoiding and/or removing timing hazards is challenging in synchronous CAD flows as process, temperature, and voltage variations become significant in submicron integrated circuits. Current CAD systems lack the capability to robustly accommodate timing closures.
The technology provides extremely robust circuits, which can accommodate a large range of supply voltages (from near threshold to high voltage), process variation, and temperature deviations, as well as severe inter-bit skews and unknown communication times, with full and correct operation. Such circuit styles have been used experimentally by NASA and others, to explore robust operation in the presence of extreme and variable environments. Unlike synchronous designs, minimal effort needs to be expended on enforcing timing closure: the designs are correct by construction over wide ranges of operating conditions.
This technology provides an algorithm that optimizes asynchronous dual-rail circuits (e.g. NULL conventional logic circuits) with respect to area, number of logic gates, or delay of the circuit by local relaxation of input completeness. In addition, this technology provides a computer-readable medium containing a set of instructions to form an asynchronous logic network.
Patent Issued (US 7,729,893)
IR M06-098
Licensing Contact: Greg Maskel