This technology describes a technique to minimize information loss associated with quantization and rounding errors as well as enhance the signal-to-noise ratio for fixed-point digital signal processors (DSPs).
Current DSPs are available either with a floating-point or fixed-point design. Floating-point DSPs offer a large dynamic range that increases the possible range for the incoming signal, but suffer from a loss of precision at large signal values and are complex and resource expensive. While fixed-point DSPs are preferred to floating-point DSPs because they are cheaper and simpler to implement, fixed-point DSPs suffer from overflow error when values exceed the maximum of the fixed range and rounding error when dealing with signals at the lower bound, leading to loss in fidelity of the processed signal. As such, there is a need for fixed-point DSPs that can be used in applications where the range of a signal’s value varies.
This technology describes a fixed-point DSP that utilizes “companding” (resizing of the incoming signal) to optimize the performance of the fixed-point processor. The device consists of an analog-to-digital converter (ADC) that digitizes the analog input signal and feeds it to the DSP, and a digital-to-analog converter (DAC) that takes the DSP output and converts it back to analog. In addition to the ADC-DSP-DAC, a signal companding circuit is coupled in parallel to the processors. This circuit samples the signals where they are largest, reducing error introduced by the multiplying controller. The controller resizes the signals to the upper range of the fixed-point DSP window in order to minimize rounding error, while avoiding overflow error from exceeding the maximum. The output signal is then resized to the original magnitude. By avoiding overflow error and minimizing rounding error, this technology improves on the capabilities of standard fixed-point DSPs.
Patent Issued (US 7,602,320)
IR M05-040, M06-069
Licensing Contact: Greg Maskel