This technology is a multi-phase clock generator that uses an injection-locked ring oscillator with a quadrature delay-locked loop for high-speed digital communication
Serial data communication requires clock and data recovery to avoid loss of data integrity when receiving data. Multi-phase clock generators have been used to produce clocks with the same frequency and fixed phase difference as the input clock, but current multi-phase clock generators have tradeoffs between accuracy, noise, and power consumption. Improvements in clock generator architecture may lead to faster and more efficient digital communication.
This technology uses a multi-phase injection-locked ring oscillator with a quadrature delay-locked loop to generate highly accurate and low-noise clocks. A prototype 8-phase clock demonstrated ideal phase accuracy (<0.5° IQ; <0.7° 8-phase), low integrated jitter (58.8fsrms from 100kHz to 1GHz) and low FOM jitter (-252.7dB) in a mature 65nm technology. This technology can be used as a staple chipset interface in many serial link communication circuits.
This technology has been validated with a proof-of-concept prototype.
IR CU21099
Licensing Contact: Greg Maskel
