Reconfigurable AI accelerator for power-constrained edge devices
This technology is a Field-programmable systolic-array (FPSA), a specialized compute primitive for embedded FPGA fabrics, designed to accelerate AI workloads in resource-constrained systems
Unmet Need: Accelerated AI workloads in resource-constrained systems
Embedded and edge systems demand high performance AI acceleration under tight constrains on power, silicon area, and cost. The use of Edge-AI in resource-constrained systems therefore requires both efficiency and post-deployment adaptability. ASIC-based accelerators deliver high performance and efficiency but lack flexibility and are costly to redesign. Existing FPGAs offer reconfigurability but remain too inefficient for practical AI deployment. To fully enable adaptive AI functions in power, area, and cost-constrained systems, there is a need for both high performance and post-manufacturing flexibility.
The Technology: Field-programmable systolic-array (FPSA) to accelerate AI workloads in resource-constrained systems
This technology is a Field-programmable systolic array (FPSA), a specialized compute primitive for embedded FPGA fabrics, designed to accelerate AI workloads in resource-constrained systems. The FPSA is optimized for tensor-style computations and reduces interconnect pressure and non-compute overhead through a hierarchical organization. This technology combines the efficiency gains of systolic-array organization with the flexibility of reconfigurable logic to meet the demands of resource-constrained systems.
Applications:
- Low-power embedded AI for consumer electronics and mobile devices
- Autonomous vehicle perception and control
- Robotics and autonomous machines
- Adaptive neural signal processing for brain-computer interfaces
- Edge AI acceleration for predictive maintenance in smart manufacturing
- Low-power embedded AI for healthcare and medical device diagnostics
Advantages:
- Enables efficient and adaptable AI acceleration in embedded and edge systems
- Designed specifically for embedded FPGA power, performance, and area constrains
- Improves routability, utilization, and scalability by lowering interconnect pressure
- Supports concurrent operation on independent data partitions
- Reduces non-compute overhead at the primitive boundary
- Improves performance and suitability for Edge-AI acceleration
Lead Inventor:
Related Publications:
Tech Ventures Reference:
IR CU26320
Licensing Contact: Greg Maskel