A compact, alias-free, and energy-efficient analog-to-digital converter for integrated electronics

Converting an analog signal to digital signal (ADC) is necessary to process continuously variable data within digital constraints. However, changing analog signals, such as voltage or light intensity, into discrete information using conventional clocked ADCs can pose problems such as aliasing, high energy consumption, and silicon real-estate costs within integrated circuits. This technology proposes a new system and method for clockless level-crossing sampling and reconstruction that provides a low cost option for analog to digital conversion with minimal area and power. This technology does not suffer from aliasing and does not require an anti-aliasing filter.

Clockless level-crossing sampling using an asynchronous modulator with novel feedback path reduces power consumption with less chip area while retaining precision

This technology implements improvements to the previous generation of asynchronous delta modulators. A single-bit digital-to-analog converter (DAC), implemented using a series of switches, replaces the N-bit feedback DAC of such delta modulators. Unlike asynchronous sigma-delta modulators, the architecture produces no output in the absence of an input signal, greatly reducing power consumption without complex power-down schemes and provides a significantly reduced loop delay, increasing the possible frequency of operation with better resolution and without slope overload. Resolution is easily controlled by a single reference voltage, offering high tunability compared to other asynchronous modulators. This clockless architecture means no aliasing in the spectrum, and no quantization noise, resulting in a higher signal-to-noise-and-distortion ratio (SNDR) than Nyquist-sampling ADCs for a given resolution. The ADC shapes the quantization error with a differentiator transfer function, resulting in low in-band distortion and noise, and hence, a high SNDR.

The technology has been tested via extensive simulations and testing of chips using various input signals. It requires no anti-aliasing filter, making the circuit extremely power efficient and compact. It can also be easily interfaced with event-driven continuous-time digital signal processing (DSP).

Lab Director:

Yannis Tsividis, Ph.D.

Applications:

• Sensors for environmental data such as temperature, pressure, light intensity, pH, etc.
• Biomedical solutions, especially diagnostic equipment
• High-frequency communication devices, e.g., radio receivers
• Speech recognition
• Digital imaging
• Voltage to frequency converters (VFCs)

Advantages:

• Compact device
• Reduced energy consumption
• Alias-free and requires no anti-alias filter
• Decreased feedback delay suitable for higher frequency applications
• Simpler architecture for easy manufacturing implementation and stability
• Tunability broadens the number of available applications
• Power dissipation scales with input characteristics, e.g., amplitude, with low standby power
• Quantization error shaping

Patent Information:

Patent Pending (US 20150365098)

Tech Ventures Reference: IR CU14248

Related Publications:

• B. Schell, Y. Tsividis. “A clockless ADC/DSP/DAC system with activity-dependent power dissipation and no aliasing,” IEEE ISSCC Digest of Technical Papers; 2008 Feb.

• C. Weltin-Wu, Y. Tsividis. “An event-driven clockless level-crossing ADC with signal-dependent adaptive resolution.” IEEE Journal of Solid-State Circuits, 2013 Sept; 48(9), pp.2180-2190.