This technology is a digital in-memory random-access memory (SRAM) architecture that enhances the computational time and resiliency for computational neural networks use in artificial intelligence (AI) applications.
The implementation and use of artificial intelligence (AI) in electronics and computing is expected to revolutionize numerous industries and experience exponential growth and demand. Current computational architecture systems to run convolutional neural networks and AI algorithms can be extremely taxing to the system, resulting in severe energy losses and heat buildup. This can damage the computer systems and also generation life-threatening situations if failure occurs in applications such as autonomous vehicles and medical devices. Advanced computational systems are urgently needed to handle process, voltage, and system fluctuations which are encountered with AI systems.
This technology is a digital in-memory computing (IMC) static random-access memory (SRAM) architecture which can support heavy loads of AI algorithms and computational neural network models. This technology reduces the number of transistors and devices in the circuit to improve area-efficiency while maintaining benefits of reduced variability of analog-mixed-signal (AMS) circuits. It can be integrated into hardware to accelerate the execution of these AI algorithms with high area and energy efficiency. This permits the system to withstand fluctuations in voltage, temperature, and process flow which could hinder ordinary computer architectures in the execution of high volumes of AI algorithms.
Patent Pending (US20230266943)
IR CU22064
Licensing Contact: Greg Maskel
