Analog-to-digital converters (ADCs) are necessary to digitize real world signals and are crucial components in many electronic devices and sensors. Pipelined ADCs, which offer an attractive trade-off between speed, power consumption, and size, have emerged as the ADC of choice for high-speed applications, including video recorders, medical imaging, and consumer electronics. However, as the electronics industry moves towards sub-micron chip sizes, pipelined ADCs are increasingly hindered by power-hungry buffers and large decoupling capacitors. This technology is a pipelined ADC design with a modified input stage to circumvent the need for a reference buffer. By eliminating the power and space requirements of the buffer, this technology provides a compact, low-power implementation of ADC operation.
To date, the majority of pipelined ADC research has focused on power-efficient ways for inter-stage signal amplification. This technology, however, focuses on the power efficiency of the multiplying digital-to-analog converter (MDAC) that serves as the input block to the ADC. A zero-crossing MDAC stage has been modified to include a reference pre-charge technique, which allows the reference voltage buffer to be replaced by simple current sources. This ADC will still retain the resolution traditionally provided by the reference buffer while consuming less power and requiring less space. This design may thus be used as a compact, power-efficient ADC design.
A prototype of this ADC design has been fabricated using a low leakage CMOS process onto an area of less than 1 mm2. Initial testing has demonstrated high resolution (11.7 bit) without requiring reference buffer power consumption.
Tech Ventures Reference: IR M11-057