Existing wireless systems operate in half duplex, where transmitted and received signals are separated in either frequency or time. Full duplex (FD) communication has the capacity to significantly increase wireless communication speed and efficiency because it utilizes the same frequency band to both transmit and receive signals. Currently available FD devices either experience a large amount of self-interference or require bulky off-the-shelf components, rendering them incompatible for CMOS implementations. This technology is a robust FD wireless communication system with a self-interference cancelling (SIC) process that can be fabricated using conventional CMOS technology. The technology provides low-cost and efficient means to a FD wireless network. As such, the technology can be incorporated into multiple input, multiple output (MIMO) technology to improve spectral efficiency for next generation wireless communication devices.
This technology incorporates a SIC method that uses specialized amplifiers in the antenna, analog, and digital domains. The multi-domain approach allows for a superior SIC compared to other FD systems using SIC within a single domain. A joint SIC ensures large overall self-interference suppression and allows one to design the amount of SIC and the SIC bandwidth for various applications. This technology uses a compact form-factor that can be integrated on a single chip. The use of cost-effective CMOS technology will enable widespread implementation of FD communication.
A prototype of the technology has been implemented in 65 nm CMOS technology and has demonstrated a record-high SIC of 85 dB.
Tech Ventures Reference: IR CU16171