This technology is a CMOS-based imaging array with single-photon avalanche diodes (SPADs) and on-chip timing circuitry for high-speed fluorescence lifetime imaging microscopy (FLIM) using time-correlated single photon counting (TCSPC).
Current fluorescence lifetime imaging microscopy (FLIM) systems using time-correlated single photon counting (TCSPC) are limited to capture rates of at most 7 frames per second in conventional applications or require several seconds per image for high-resolution scanned imaging. These slow acquisition speeds prevent observation of dynamic biological processes and limit throughput for screening applications. Additionally, existing FLIM systems consist of large, expensive modular units that lack portability and require complex external readers for data acquisition and processing.
This technology is a CMOS-based imaging array consisting of a 64 x 64 pixel array of single-photon avalanche diodes (SPADs) integrated with independent time measurement circuitry on a single CMOS chip, fabricated in 130-nm technology. Each pixel achieves photon arrival time measurements using delay-locked loop (DLL) based time-to-digital converters with sub-70 picosecond timing resolution and a 64-nanosecond range. The system utilizes a custom high-speed data path specifically designed for the sparse photon detection characteristic of FLIM measurements, allowing for data transmission rates of up to 42 Gbps via parallel low-voltage differential signaling drivers. The integrated design enables wide-field FLIM imaging at 200 frames per second or high-resolution (256×256) scanned imaging at up to 20 frames per second.
Patent Issued (US 9,831,283)
IR CU12003
Licensing Contact: Greg Maskel