Lead Inventors:
Luca Carloni,
Keren Bergman
On-Chip Electronic Networks Power Requirements Growing
Chip manufacturers, in order to achieve greater gains in processing power while lowering power requirements and costs, are moving away from single core processors toward multicore processors. Processors with eight cores or more have been realized. Performance gains will continue to come from even greater increases in the number of processor cores per chip. As a result, the architecture of multicore processors has begun to mimic that of multiprocessor devices leading to a significant bottleneck in the intrachip communications infrastructure. Current research has focused on the use of electronic networks, which have the bandwidth to replace traditional links. On-chip electronic networks consume increasing amounts of power and the scalability of the network is limited by the ability to dissipate power.
This technology is a device for on-chip data communication that utilizes interconnected optical switches to move data between processors. This innovation offers better performance-per-watt communications than electronic switches while also giving better bandwidth capacity and scalability.
On-Chip Data Communication with Increased Per-Watt Performance, Bandwidth Capacity and Scalability
This invention is an on-chip data communication infrastructure employing interconnected optical switches. Each optical switch includes one or more photonic switching elements under the control of a corresponding electronic router. As a result, an optical path is constructed as the electronic path setup message is routed to the destination. Once the path is constructed, data is converted from the electronic domain to the optical domain, sent along the optical path through the optical switches, and converted from the optical domain to the electronic domain at the destination.
Photonic interconnection networks are well suited to bulk data transfer. They offer low power dissipation that remains independent of bandwidth capacity while providing ultra-high throughputs and minimal access latencies. In this way, photonic networks can be scaled to meet the growing demands for high bandwidth, on-chip communications, such as communications between multiple cores. These networks realize power savings by transmitting data end to end without the need for repeating, regeneration or buffering once the optical path is set up. A comparison of power consumption in a photonic Network-on-chip (NoC) and an electronic NoC, each designed to provide the same bandwidth to the same number of cores, demonstrates that the power expended on intrachip communications is two orders of magnitude less in optical networks. Moreover, the photonic network can be expanded to achieve even greater throughput performance without requiring additional power, as the consumed power scales with the length of the optical path, not with the number of parallel optical links.
Applications:
• Multi-core chip design and manufacturing
• Other power sensitive data handling applications (e.g. routers)
Advantages:
• Lower power dissipation
• High bandwidth capacity
• Scalable without loss of performance or increase in power consumption
Opportunities
• Licensing of technology for use in chip design/production
Patent Status: Patent Pending (
WO/2008/080122)
Publications:
IEEE Transactions on Computers, vol. 57, no. 9, pp. 1246-1260, 2008.
