Computing processes in computers, cell phones and other electronics are carried out by microprocessors on integrated circuits. Increasingly, multiple processors are being utilized on a single chip to improve device performance. Communication delays and power dissipation issues, however, increase with additional processors. This technology utilizes a photonic network-on-chip system to achieve low power, high-speed communication within a chip. Further, this technology integrates with existing CMOS architectures and achieves high bandwidth, allowing increasingly more processors to be added onto a single chip while maintaining high data speeds and high bandwidth at low power consumption.
This technology utilizes optical resonators in place of electronic switches for optical data communication. In traditional electronic network-on-chips, data is often rerouted, buffered and regenerated several times before reaching its destination. With optical communication, data can be transmitted end to end without any rerouting or disturbances, as there are no photonic storage elements. As such, high communication speeds between processors are achievable with this technology. Power consumption in this photonic architecture is lower because unlike electronic switches, photonic switches turn on/off after every message, not every transmitted bit. Additionally, power dissipation is independent of transmission distance in the optical waveguides.
A prototype of the technology has been simulated and been shown to deliver high speed communication within chip multiprocessor architectures while expending low power.
Patent Issued (US 8,340,517)
Tech Ventures Reference: IR M08-035