This technology is a twin phase interpolator circuit design with a delta quadrature delay-locked loop for low jitter, linear serial data communication over a wide frequency bandwidth.
Multi-phase clock generators and clock interpolators are critical in all high-performance analog/digital and fully digital circuits for serial communication. Current methods for serial data transfer are limited by their limited frequency range, high power consumption, and insufficient levels of linearity. This in turn limits the maximum rate of data transfer.
This circuit architecture uses a delta quadrature delay-locked loop with twin phase interpolators for serial data communication. This architecture has a high operational frequency range, high phase linearity for accurate timing, and low power usage, due in part to its low parasitic capacitance at the output nodes and its small circuit footprint.
This technology has been validated with measurements of prototype circuits.
Patent Pending
IR CU22025
Licensing Contact: Greg Maskel