Columbia Technology Ventures

Phase interpolator for efficient serial data communication

This technology is a twin phase interpolator circuit design with a delta quadrature delay-locked loop for low jitter, linear serial data communication over a wide frequency bandwidth.

Unmet Need: High-linearity phase interpolators for high-speed, accurate data transfer

Multi-phase clock generators and clock interpolators are critical in all high-performance analog/digital and fully digital circuits for serial communication. Current methods for serial data transfer are limited by their limited frequency range, high power consumption, and insufficient levels of linearity. This in turn limits the maximum rate of data transfer.

The Technology: Twin phase interpolators for wide bandwidth, linear serial communication

This circuit architecture uses a delta quadrature delay-locked loop with twin phase interpolators for serial data communication. This architecture has a high operational frequency range, high phase linearity for accurate timing, and low power usage, due in part to its low parasitic capacitance at the output nodes and its small circuit footprint.

This technology has been validated with measurements of prototype circuits.

Applications:

  • Wireless and wireline transceivers
  • Optical and electrical transceivers
  • High-speed data transfer
  • Self-driving cars and other AI-based services
  • Research tool for more efficient circuit development

Advantages:

  • Low power
  • Preserves data integrity
  • Small footprint for reduced resource consumption
  • High frequency bandwidth
  • Low noise

Lab Director:

Peter Kinget, Ph.D.

Patent Information:

Patent Pending

Related Publications:

Tech Ventures Reference: