Photonic networks-on-chip for optimizing high-performance microprocessors
This technology is a combined electronic/photonic networks-on-chip system to optimize microprocessor performance and power consumption.
Unmet Need: Performance-per-watt optimized chip multiprocessor
Current direct memory access (DMA) communications utilize chip multiprocessors, which store multiple processor cores on one chip. While this architecture improves performance, it also creates data congestion within the chip. Networks-on-chip (NoC) approaches offer an opportunity to improve efficiency, however, current methods are constrained by a fixed upper limit to chip power dissipation.
The Technology: Hybrid photonic/electronic networks-on-chip for optimal chip performance
This technology uses photonic NoC, which maintain the low latency and high bandwidth of a traditional NoC, while also consuming minimal amounts of power. In contrast to electronic networks, optical networks are more energy-efficient and can process larger amounts of data but are less flexible and unable to buffer. The hybrid architecture of this chip comprises both electronic and optical networks, combining the bandwidth advantage of optical networks and the processing capacity of electronics, thus optimizing chip performance-per-watt.
This technology has been validated using an event driven stimulator and a comparative power analysis of a photonic versus an electronic NoC.
Applications:
- Direct memory access communications
- Other high-performance networks
- Technologies requiring fast computing or data retrieval
Advantages:
- High capacity
- High transparency
- Minimal access latency
- Low power consumption
Lead Inventor:
Patent Information:
Related Publications:
Tech Ventures Reference:
IR M08-034
Licensing Contact: Greg Maskel