Ultra-low-power multiplying digital-to-analog conversion architecture for high energy efficiency circuit applications
Pipelined analog-to-digital converters (ADCs) are widely used in circuit applications requiring high energy efficiency and small circuit area. The standard implementation of a pipelined ADC using an operational transconductance amplifier (OTA) introduces power inefficiency when performing signal sampling. This technology is a multiplying digital-to-analog conversion (MDAC) architecture that uses current-charge-pumps (CCPs) and comparators to reduce power demand. By avoiding the use of both interstage OTAs and power-hungry reference buffers, this MDAC design exhibits significantly lower power consumption than comparable technologies.
Significant power reduction achieved using current-charge-pump residue amplification and comparators
Pipelined ADCs consist of several stages that each produce digital output bits and compute/amplify the residue signal before passing it on to the next stage. Most pipelined ADC designs implement the high gain OTA to amplify the residue signal of each stage or employ power-hungry reference buffers to drive the capacitors used to sample the input of each stage. In contrast, the MDAC design proposed here uses only switches, current sources, capacitors, and a comparator. It occupies a small circuit area and achieves high power efficiency by eliminating OTAs for the interstage amplification and by avoiding power-hungry buffers for the reference voltages.
Proof-of-concept was demonstrated using a CCP pipelined ADC prototype in a 90-nm CMOS.
Lab Director:
Patent Information
- Low-power wireless and wired communication and signal processing circuits
- Scientific instruments requiring low-power consumption
- Music recording devices
- Video signal processing
- Medical imaging
Advantages:
- Reduces the power requirements of pipelined ADCs
- Achieves high energy efficiency
- Occupies a small circuit area
Patent Information:
Tech Ventures Reference: IR M11-045