A compact, alias-free, and energy-efficient analog-to-digital converter for integrated electronics
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Peter Kinget
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Removal of the reference buffer reduces both the power consumption and size of the ADC. This ADC will still retain the resolution traditionally provided by the reference buffer while consuming less power and requiring less space. Analog-to-digital converters (ADCs) are necessary to digitize real world signals and are crucial components in many electronic devices and sensors.
The standard implementation of a pipelined ADC using an operational transconductance amplifier (OTA) introduces power inefficiency when performing signal sampling. The standard implementation of a pipelined ADC using an operational transconductance amplifier (OTA) introduces power inefficiency when performing signal sampling. This technology is a multiplying digital-to-analog conversion (MDAC) architecture that uses current-charge-pumps (CCPs) and comparators to reduce power demand.
This technology is a multi-phase clock generator that uses an injection-locked ring oscillator with a quadrature delay-locked loop for high-speed digital communication. Multi-phase clock generators have been used to produce clocks with the same frequency and fixed phase difference as the input clock, but current multi-phase clock generators have tradeoffs between accuracy, noise, and power consumption. Improvements in clock generator architecture may lead to faster and more efficient digital communication.
- 4CMOS
- 3Wideband
- 265 nm process
- 2Data integrity
- 2Digital electronics
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- 8Electronics
- 5Electronic circuits
- 5Telecommunications
- 4Telecommunications engineering
- 3Radio communications
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- 8Peter Kinget
- 6Harish Krishnaswamy
- 4Yannis Tsividis
- 3Aurel Lazar
- 3Jin Zhou
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- 8Greg Maskel
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- 8Electrical Engineering
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- 8Fu Foundation School of Engineering and Applied Science (SEAS)
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